1. Technical Field
The present invention relates to a semiconductor device, and more particularly, to an input receiver of a semiconductor device.
2. Description
Semiconductor devices include input receivers to receive input data from outside the device. Nowadays, as the operation speed of semiconductor devices increases, the sense speed, i.e., the operation speed of input receivers, has to be increased. In the field of DRAMs, in order to improve operation speed, single data rate (SDR) synchronous DRAMs and dual data rate (DDR) synchronous DRAMs that are operated at a speed of hundreds of MHz have been developed. An SDR synchronous DRAM receives an input signal in response to a rising edge of a clock signal and a DDR synchronous DRAM receives an input signal in response to a rising edge and a falling edge of a clock signal.
FIG. 1 is a circuit diagram illustrating an input receiver used in an SDR synchronous DRAM. Referring to FIG. 1, the input receiver includes a pre-amplifier 11, a sense amplifier 13, and a latch circuit 15. Here, the pre-amplifier 11 amplifies an input signal IN, from outside of the DRAM, with reference to a reference voltage VREF. The sense amplifier 13 amplifies an output signal POUT, and an inverted output signal POUTB, of the pre-amplifier 11 in response to a clock signal CLK, i.e., a rising edge of the clock signal CLK. The latch circuit 15 latches an output signal SOUT, and an inverted output signal SOUTB, of the sense amplifier 13 to output a final output signal OUT and an inverted final output signal OUTB.
FIG. 2 is a circuit diagram illustrating an input receiver used in a DDR synchronous DRAM and a RAMBUS(copyright) DRAM. Referring to FIG. 2, the input receiver includes a first pre-amplifier 11a, a first sense amplifier 13a, a first latch circuit 15a, a second pre-amplifier 11b, a second sense amplifier 13b, and a second latch circuit 15b. Since DDR synchronous DRAMs and RAMBUS(copyright) DRAMs have to receive input signals IN at a rising edge and a falling edge of a clock signal CLK, the input receiver used in the DDR synchronous DRAM and the RAMBUS(copyright) DRAM includes two pre-amplifiers 11a and 11b, two sense amplifiers 13a and 13b, and two latch circuits 15a and 15b. 
The configurations of the first and second pre-amplifiers 11a and 11b are the same as that of the pre-amplifier 11 of FIG. 1, and the first and second pre-amplifiers 11a and 11b amplify an input signal IN from outside of the DRAM with reference to reference voltages VREF, respectively. The first sense amplifier 13a amplifies an output signal POUT1, and an inverted output signal POUTB1, of the first pre-amplifier 11a in response to a clock signal CLK, i.e., a rising edge of the clock signal CLK. The second sense amplifier 13b amplifies an output signal POUT2, and an inverted output signal POUTB2, of the second pre-amplifier 11b in response to an inverted clock signal CLKB, i.e., a falling edge of the clock signal CLK. The first latch circuit 15a latches an output signal SOUT1, and an inverted output signal SOUTB1, of the first sense amplifier 13a to output a final output signal OUT1 and an inverted final output signal OUTB1. The second latch circuit 15b latches an output signal SOUT2, and an inverted output signal SOUTB2, of the second sense amplifier 13b to output a final output signal OUT2 and an inverted final output signal OUTB2.
Here, the sizes of NMOS transistors N11, to which the reference voltages VREF are applied, in the pre-amplifiers 11, 11a, and 11b of the conventional input receivers of FIGS. 1 and 2 are fixed. Accordingly, a sense speed, i.e., an operating speed, is uniform regardless of the voltage level of the input signal IN.
FIG. 3 is a circuit diagram illustrating another input receiver used in a DDR synchronous DRAM and a RAMBUS(copyright) DRAM. Referring to FIG. 3, the input receiver includes a first pre-amplifier 31a, a first sense amplifier 33a, a first latch circuit 35a, a second pre-amplifier 31b, a second sense amplifier 33b, and a second latch circuit 35b. An output signal OUT2 of the second latch circuit 35b is fed back and applied to the gate of an NMOS transistor N31 in the first pre-amplifier 31a, and an output signal OUT1 of the first latch circuit 35a is fed back and applied to the gate of an NMOS transistor (not shown) in the second pre-amplifier 31b. 
However, when the input signal IN, the output signal OUT2 of the second latch circuit 35b, and the data OUT1 stored in the first latch 35a have the logical values of 1, 1, and 0, respectively, a sense speed, i.e., an operating speed, is lowered in the input receiver of FIG. 3.
To solve the above-described problems, it would be desirable to provide an input receiver with an improved sense speed.
In one aspect of the invention, an input receiver includes a pre-amplifier adapted to control an offset voltage in response to a feedback signal and adapted to amplify an input signal with reference to a reference voltage. A sense amplifier amplifies an output signal and an inverted output signal of the pre-amplifier in response to a clock signal. A latch circuit latches an output signal and an inverted output signal of the sense amplifier. An inversion circuit uses the reference voltage as a power supply voltage and inverts an inverted output signal of the latch circuit. In addition, an output signal of the inversion circuit is supplied as the feedback signal.
Alternatively, the output signal of the latch circuit may be directly supplied to the pre-amplifier as the feedback signal while not using the inversion circuit.
The pre-amplifier includes a first load transistor, a second load transistor, and first through third transistors. Here, the first load transistor is connected between a first reference voltage and an inversion output terminal outputting the inverted output signal in the pre-amplifier. The second load transistor is connected between the first reference voltage and an output terminal outputting the output signal in the pre-amplifier. While the gate of the first transistor receives the input signal, the first transistor is connected between the inversion output terminal and a common node. While the gate of the second transistor receives the reference voltage, the second transistor is connected between the output terminal and the common node. While the gate of the third transistor receives the feedback signal, the third transistor is connected between the output terminal and the common node. Here, the sizes of the first through third transistors are different from each other.
The common node is connected to a second reference voltage or the pre-amplifier further includes a fourth transistor connected between the common node and the second reference voltage while a gate receives an enable signal.
In another aspect of the invention, an input receiver includes a first pre-amplifier adapted to control an offset voltage in response to a first feedback signal and adapted to amplify an input signal with reference to a reference voltage, and a second pre-amplifier adapted to control an offset voltage in response to a second feedback signal and adapted to amplify the input signal with reference to the reference voltage.
A first sense amplifier amplifies an output signal and an inverted output signal of the first pre-amplifier in response to a clock signal. A first latch circuit latches an output signal and an inverted output signal of the first sense amplifier. A first inversion circuit uses the reference voltage as a power supply voltage and inverts an inverted output signal of the first latch circuit. Here, the output signal of the first inversion circuit is supplied as the first feedback signal. A second sense amplifier amplifies an output signal and an inverted output signal of the second pre-amplifier in response to an inverted clock signal. A second latch circuit latches an output signal and an inverted output signal of the second sense amplifier. A second inversion circuit uses the reference voltage as a power supply voltage and inverts an inverted output signal of the second latch circuit.
Alternatively, the output signal of the first latch circuit may be supplied to the first pre-amplifier as the first feedback signal while not using the first inversion, circuit and the output signal of the second latch circuit may be supplied to the second pre-amplifier as the second feedback signal while not using the second inversion circuit.
Beneficially, the constitutions of the first and second pre-amplifiers are the same as that of the pre-amplifier of the first embodiment. The constitutions of the first and second sense amplifiers are the same as that of the sense amplifier of the first embodiment. The constitutions of the first and second latch circuits are the same as that of the latch circuit of the first embodiment.